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Overview

The PCIe Gen 6 PHY IP Core is a high-performance, silicon-proven physical layer interface that supports 64 GT/s per lane using advanced PAM4 signaling. Fully compliant with the PCI Express 6.0 specification, it is engineered for low latency, power efficiency, and robust signal integrity—ideal for next-generation ASICs, SoCs, and multi-die architectures.

Our PCIe Gen 6 IP Core is designed to meet the demands of cutting-edge systems, ensuring low latency, high throughput, and robust interoperability across platforms, enabling the next generation of computing and networking solutions.

  • PCIe 6.0 Compliance: Full support for 64 GT/s PAM-4 signaling.
  • Low Latency & High Throughput: Optimized for minimal latency and maximum bandwidth.
  • Forward Error Correction (FEC) & Decision Feedback Equalization (DFE): Ensures reliable data transmission and signal integrity.
  • Integrated CDR and Low-Jitter PLLs: Improves timing accuracy and link quality.
  • Power Efficiency: Supports L0p, L1, and L2 power-saving modes for energy-optimized systems.
  • Scalable Lane Support: Configurations for x1, x4, x8, and x16 available.
  • Seamless Integration: Designed for tight coupling with PCIe Gen 6 Controller IP.
  • Robust Signal Integrity Tools: Includes eye diagram analysis, jitter measurement, and compliance testing.
  • Retimer and Redriver Support: Compatible with signal conditioning elements for extended reach.
  • Customizable PIPE Interface: Adaptable SerDes and protocol interface layer.
  • High Bandwidth Efficiency: 64 GT/s with superior signal fidelity for maximum data throughput.
  • Power Optimization: Supports dynamic power gating and low-energy modes for energy-efficient designs.
  • Seamless Integration: Engineered to work effortlessly with PCIe Gen 6 Controller IP.
  • Low Latency & Determinism: Supports FLIT mode, enabling fixed packet timing and predictable data delivery.
  • Reliability: Combines PAM-4 signaling with Forward Error Correction (FEC) to maintain robust communication in high-noise environments.
  • Future-Ready: Backward compatible with PCIe Gen 1 through Gen 5, and built for next-gen workloads.
  • High-Performance Computing (HPC): Enables low-latency, high-bandwidth communication for compute-intensive workloads.
  • Data Center Accelerators & AI Chips: Connects CPUs, GPUs, and AI accelerators for optimized inference and training pipelines.
  • SmartNICs and Networking Equipment: Supports low-latency data processing and high-speed packet forwarding.
  • SSD & NVMe Storage Controllers: Delivers fast access to high-throughput, low-latency storage systems.
  • PCIe Switches & Expansion Devices: Facilitates scalable system architectures with flexible connectivity.
  • Edge Computing Platforms: Brings high-speed, efficient interconnects to distributed edge environments.
  • Arm®-based SoCs: Seamless integration for heterogeneous compute platforms.
  • Intel® FPGAs & SoCs: Support for Stratix and Agilex families.
  • Xilinx® FPGAs: Compatible with Versal and UltraScale+™ architectures.
  • ASIC Integration: Portable across TSMC, GlobalFoundries, and Samsung process nodes.
  • RISC-V Platforms: Flexible deployment with native PCIe support.
PCIe Gen 6 Controller IP Core
CXL 1.0
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