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Overview

Compute Express Link (CXL) 1.0 is a high-speed, low-latency interconnect standard built on top of the PCIe 5.0 physical layer, designed to enhance communication between CPUs and accelerators, memory, or I/O devices.

The CXL 1.0 IP Core enables efficient cache coherency and memory sharing, offering a unified interface for heterogeneous computing systems. It supports three sub-protocols—CXL.io, CXL.cache, and CXL.mem—to provide coherent and non-coherent access, allowing devices to share memory resources seamlessly and efficiently.

  • Compliance with CXL 1.0 Specification: Supports all three sub-protocols: CXL.io, CXL.cache, and CXL.mem
  • Low-Latency Cache-Coherent Interconnect: Enables host processors to access device memory with full coherency
  • High Bandwidth, PCIe 5.0 Physical Layer Support: Leverages PCIe 5.0 PHY, supporting up to 32 GT/s per lane
  • Flexible Endpoint Configurations: Supports Type 1, Type 2, and Type 3 device modes
  • Seamless Integration: Compatible with leading FPGA platforms and SoC environments
  • Multi-Lane Scalability: Configurable x4, x8, or x16 link widths
  • Power and Reset Management: Implements standard power state transitions and reset controls
  • Verification and Compliance Tested: Comes with pre-verified test benches, monitor modules, and simulation support
  • Enables shared memory architecture between host and device
  • Reduces data movement overhead for AI and HPC workloads
  • Minimizes latency while maximizing bandwidth utilization
  • Simplifies system design with cache coherence and memory pooling
  • Leverages the widely adopted PCIe 5.0 infrastructure
  • Enhances resource efficiency and system scalability
  • Facilitates the development of heterogeneous compute platforms
  • AI & Machine Learning Accelerators
  • Memory Expansion Modules
  • Cloud-native Data Centers
  • High Performance Computing (HPC) Clusters
  • Security and Network Offload Devices
  • FPGAs: Intel Stratix 10, Intel Agilex, Xilinx Versal, AMD/Xilinx UltraScale+
  • ASIC/SOC: Easily synthesizable in standard design flows
  • PHY Support: Requires compliant PCIe Gen5 PHY
PCIe Gen 6 PHY
CXL 2.0
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