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Overview

The MIPI DisplayPort 2.0 IP Core is a next-generation high-speed display interface IP solution designed to meet the increasing demands for ultra-high-resolution video, multi-stream support, and power efficiency across a broad spectrum of devices.

Built on the latest DisplayPort 2.0 specification from the Video Electronics Standards Association (VESA), it delivers enhanced data bandwidth, flexible protocol layers, and superior display quality—all while supporting MIPI PHY standards such as M-PHY for mobile and embedded applications.

  • Compliant with VESA DisplayPort 2.0 Specification: Backward compatible with DP 1.4a and earlier and supports main link rates: UHBR 10 (10 Gbps), UHBR 13.5 (13.5 Gbps), and UHBR 20 (20 Gbps).
  • MIPI M-PHY and VESA AUX Channel Support: Integration with MIPI M-PHY v4.1/v5.0 for mobile SoCs and AUX Channel and sideband communication fully supported.
  • Massive Bandwidth Capability: Up to 80 Gbps aggregate bandwidth using 4 lanes of UHBR20. Suitable for 8K @ 60Hz, 4K @ 240Hz, or multiple simultaneous 4K displays.
  • Display Stream Compression (DSC) and Forward Error Correction (FEC): Enhanced image quality with reduced bandwidth consumption and reliable data delivery.
  • Multi-Stream Transport (MST) Support: Drive multiple independent displays from a single interface.
  • Panel Replay & Adaptive Sync Support: Efficient update of static images, reducing latency and improving experience in gaming and VR use cases.
  • Dual-Mode Support (DP++): Enables native HDMI and DVI output through passive adapters.
  • Hot Plug Detection (HPD) and EDID Support: Supports dynamic display connections and identification.
  • Support for Video, Audio, and Data Streams: Simultaneous transmission of HDCP-protected content, audio, and auxiliary data.
  • Highly Configurable: Scalable lane count (1, 2, or 4), with customizable main link rates and video timing parameters.
  • Platform Compatibility: FPGA and ASIC-ready with interface options including AXI, AHB, or custom bus interfaces.
  • Ultra High-Resolution Support: Perfect for 4K, 5K, and 8K displays with HDR and wide color gamut capabilities.
  • Superior Efficiency: Designed for low-power consumption and reduced EMI, critical for mobile and embedded devices.
  • Backward Compatibility: Seamless interoperability with existing DP 1.2/1.4 monitors and adapters.
  • Robust Audio/Video Delivery: Ensures synchronized transmission of high-fidelity video and multichannel audio.
  • Time-to-Market Ready: Comes with a verified testbench, sample designs, and integration support for fast deployment.
  • Fully Customizable: Lane configuration, pixel formats, and audio/video routing can be easily tailored to application-specific needs.
  • Secure & Reliable: Supports HDCP content protection and robust link integrity features.
  • Cross-Industry Use: Ideal for mobile, automotive, AR/VR, industrial, and display-centric applications.
  • Smartphones & Tablets with External Display Support
  • Augmented/Virtual Reality Headsets (AR/VR/MR)
  • Automotive In-Vehicle Displays & Infotainment Systems
  • Professional Monitors and Docking Stations
  • Wearable Tech and Smart Glasses
  • Medical and Industrial High-Res Displays
  • Gaming Devices and Consoles
  • FPGA: AMD Xilinx (Versal, Zynq UltraScale+), Intel (Agilex, Stratix 10), Lattice (CertusPro-NX), Microsemi (PolarFire)
  • ASIC: Fully synthesizable RTL for 7nm/5nm/3nm nodes
  • PHY: Supports MIPI M-PHY v4.1/v5.0, AUX & HPD channels
  • Interfaces: AXI4-Stream, AXI4-Lite, AHB/APB, custom interfaces
  • OS Support: Linux, Android, RTOS with driver integration support
MIPI DSI-2
MIPI H.264
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