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Overview

The 10G/100G MAC/PCS IP Core is a fully integrated and configurable solution that combines the Ethernet Media Access Control (MAC) and Physical Coding Sublayer (PCS) functionality into a single, high-performance IP block.

Designed in compliance with IEEE 802.3ae (10G) and IEEE 802.3ba (100G) standards, this IP core is ideal for implementing high-speed Ethernet solutions in FPGAs and ASICs for data center, telecom, AI, and networking infrastructure applications.

The IP core handles Ethernet frame encapsulation, error checking, flow control, lane alignment, and 64b/66b encoding/decoding — all with deterministic performance and minimal resource overhead.

  • IEEE 802.3ae and 802.3ba Compliant: Fully compliant with 10G and 100G Ethernet MAC and PCS specifications.
  • Integrated 64b/66b Encoding & Decoding: Implements the PCS sublayer for lane encoding, synchronization, and scrambling.
  • High-Speed Operation: Supports full-duplex operation at 10 Gbps and 100 Gbps line rates.
  • Standard Interface Support:
    • XGMII/XLGMII PHY interfaces
    • Optional AXI/AXI-Stream for user data and control interface
  • Preamble Insertion and CRC Handling: Automatic Ethernet frame preamble generation, FCS (CRC-32) calculation, and checking.
  • Pause Frame Support (802.3x): Flow control via pause frame generation and handling to manage congestion.
  • Jumbo Frame Support: Configurable support for standard and oversized Ethernet frames.
  • Low Latency & Low Resource Utilization: Pipelined architecture with minimal logic usage, optimized for performance and power.
  • End-to-End Integration: Combines MAC and PCS in one IP block, reducing design complexity and integration effort.
  • Line-Rate Performance: Achieve full throughput at 10G and 100G speeds with minimal latency.
  • Flexible & Configurable: Adaptable to different system requirements with optional features like pause frames, jumbo frames, and VLAN tagging.
  • Simplified SoC and FPGA Design: Standard interfaces and modular architecture ensure fast deployment in custom ASICs and FPGAs.
  • Robust Error Detection & Correction: Built-in CRC and synchronization mechanisms improve data integrity and transmission reliability.
  • Scalable for Next-Gen Networking: Suitable for building SmartNICs, routers, switches, and 5G infrastructure requiring high bandwidth and low latency.
  • Data Center Networking
  • SmartNIC and Network Interface Cards
  • High-Performance Computing (HPC)
  • Telecom Core and Edge Devices
  • 5G Fronthaul and Midhaul
  • Cloud Infrastructure and Servers
  • AI/ML Accelerator Interconnects
  • The IP core is verified and supported on a wide range of industry-standard platforms:
  • AMD Xilinx FPGAs – UltraScale+, Virtex, Kintex
  • Intel (Altera) FPGAs – Stratix 10, Agilex
  • ASIC Implementations – Easily portable across 7nm, 5nm, and beyond
  • Custom SoC & Chiplet Environments – Adaptable to advanced interconnect fabrics like CXL, UCIe, or Ethernet-based chiplet links
10G/100G TCP/IP
SmartNIC HFT
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