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Overview

The Compute Express Link™ (CXL) 3.0 IP Core is designed to meet the demands of next-generation heterogeneous computing systems, enabling high-speed, low-latency interconnect between CPUs, GPUs, FPGAs, DPUs, accelerators, memory expanders, and smart I/O devices.

Supporting the CXL 3.0 specification, this IP delivers backward compatibility with CXL 1.x/2.0, advanced memory pooling, and fabric capabilities, making it ideal for data centers, AI/ML workloads, and HPC environments.

  • CXL Protocol Support: CXL.io, CXL.cache, and CXL.mem coherence protocols with support for Type 1, Type 2, and Type 3 devices.
  • Backward Compatibility: Fully compliant with CXL 1.1 and CXL 2.0 for smooth ecosystem integration.
  • CXL Fabric Support: Enables fabric switching with memory pooling, multilevel switching, peer-to-peer communication, and global memory addressing.
  • High Bandwidth: Leverages PCIe 6.0 physical layer for up to 64 GT/s per lane with PAM4 signaling.
  • Scalability: Supports up to 16-lane configurations for maximum throughput and bandwidth aggregation.
  • Security Features: ECC, link integrity checks, and advanced error handling.
  • Flexible Integration: Modular design supporting multiple SoC and FPGA platforms with AXI interfaces.
  • Low Latency: Optimized for cache and memory coherence with minimal protocol overhead.
  • High Bandwidth & Low Latency: Built on PCIe 6.0, CXL 3.0 delivers up to 64 GT/s per lane, enabling fast and efficient data transfers.
  • Memory Pooling & Expansion: Dynamically share and allocate memory across devices, optimizing system resources and reducing over-provisioning.
  • Coherency Support: Full support for CXL.cache and CXL.mem protocols ensure seamless memory sharing between host and devices.
  • Fabric & Composability: Enables scalable, disaggregated architectures with peer-to-peer communication and global memory access.
  • Backward Compatible: Supports CXL 1.1 and 2.0 for easy integration with existing platforms.
  • Secure & Reliable: Features ECC, error handling, and link integrity checks for robust system performance.
  • Memory Expansion and Pooling Devices
  • AI/ML Accelerators
  • Data Center and Cloud Infrastructure
  • SmartNIC and DPU Integration
  • HPC Systems
  • FPGA: Intel, AMD/Xilinx
  • ASIC: TSMC, Samsung, GlobalFoundries
  • Host Interface: AXI4, TileLink, AHB (customizable)
CXL 2.0
PCIe Gen 5
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