Overview

The Low-Density Parity-Check (LDPC) IP Core is a high-throughput, low-latency forward error correction (FEC) engine designed to meet the rigorous requirements of next-generation communication and data storage systems. LDPC codes are known for their near-Shannon limit performance and are widely adopted in standards such as 5G NR, Wi-Fi 6/7, DVB-S2/S2X, G.hn, 10GBASE-T Ethernet, SATA, NVMe, and more.

  • Ultra-High Throughput: Achieves data rates exceeding multi-Gbps in parallel decoder configurations, with scalability for even higher throughput.
  • Flexible Code Support: Supports standard-compliant codes (e.g., 5G, DVB-S2, 802.11ax) and customizable LDPC matrices for proprietary use cases.
  • Multiple Decoding Algorithms: Includes Min-Sum, Normalized Min-Sum, Offset Min-Sum, and layered decoding approaches for performance and area trade-offs.
  • Programmable Block Sizes & Code Rates: Dynamic configuration of codeword length (up to 64K) and code rates (from 1/4 to 9/10) without re-synthesis.
  • Soft Decision Input Support: Operates on LLR (Log-Likelihood Ratio) inputs for improved decoding performance over noisy channels.
  • Simulation-Tested & Hardware Validated: Exhaustively verified under standard AWGN, fading, and burst noise channel conditions.
  • Fully Parameterizable Architecture: Allows selection of the number of iterations, input width, memory organization, and throughput level during synthesis.
  • Multi-Instance Support: Multiple decoders can be instantiated in parallel for ultra-high-speed system requirements.
  • Near-Shannon Limit Performance: Achieves outstanding error correction close to theoretical limits, improving link robustness significantly.
  • Highly Configurable: Can be adapted to multiple industry standards and tailored to custom code structures as needed.
  • Area & Power Optimized: Efficient memory usage and arithmetic optimizations ensure minimal resource footprint for embedded and portable systems.
  • Low Latency: Pipelined and iterative decoding schemes ensure real-time correction, critical for latency-sensitive applications.
  • Standards Compliance: Seamless integration with DVB-S2/S2X, Wi-Fi 6/7, 5G NR, 10G/25G/100G Ethernet, G.hn, and other protocols.
  • Secure, Reliable Communication: Enhances system-level resilience against channel-induced errors, reducing retransmission and boosting overall QoS.
  • Wireless & Cellular Communication
  • Satellite Communication
  • Storage & Memory Systems
  • High-Speed Networking
  • Defense & Aerospace
  • Test & Measurement Equipment
  • FPGA:
    • Xilinx Ultrascale / Ultrascale+, Zynq, Artix, Kintex
    • Intel Stratix, Arria, Agilex
    • Microsemi PolarFire (on request)
  • ASIC:
    • Technology support down to 7nm
    • Synthesis & place-and-route optimized netlists
    • DFT-friendly with scan, BIST hooks available
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